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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ADF4212L dual low power pll frequency synthesizer features i dd total, 7.5 ma bandwidth rf/if, 2.4 ghz/1.0 ghz 2.7 v to 3.3 v power supply separate vp allows extended tuning voltage programmable dual modulus prescaler rf and if: 8/9, 16/17, 32/33, 64/65 programmable charge pump currents 3-wire serial interface analog and digital lock detect fastlock mode power-down mode 20-lead tssop and 20-lead mlf chip scale package applications wireless handsets (gsm, pcs, dcs, cdma, wcdma) base stations for wireless radio (gsm, pcs, dcs, cdma, wcdma) wireless lans cable tv tuners (catv) communications test equipment functional block diagram 12-bit if b-counter 6-bit if a-counter if prescaler output mux if lock detect charge pump rf lock detect charge pump 14-bit rf r-counter 14-bit if r-counter oscillator 22-bit data register sdout 12-bit rf b-counter 6-bit rf a-counter rf prescaler if phase frequency detector dgnd rf a gnd rf dgnd if a gnd if v dd 1 v dd 2 v p 1 v p 2 ADF4212L if in ref in clock data le rf in cp rf muxout cp if r set reference if current setting ifcp3 ifcp2 ifcp1 reference rfcp3 rfcp2 rfcp1 reference r set fl o fl o switch rf phase frequency detector general description the ADF4212L is a dual frequency synthesizer that can be used to implement local oscillators (lo) in the up-conversion and down-conversion sections of wireless receivers and transmitters. it can provide the lo for both the rf and if sections. it con- sists of a low noise digital pfd (phase frequency detector), a precision charge pump, a programmable reference divider, programmable a and b counters, and a dual modulus prescaler (p/p + 1). the a (6-bit) and b (12-bit) counters, in conjunction with the dual modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter) allows selectable refin frequencies at the pfd input. a complete pll (phase-locked loop) can be implem ented if the synthesizer is used with external loop filters and vcos (voltage controlled oscillators). control of all the on-chip registers is via a simple 3-wire inter- face with 1.8 v compatibility. the devices operate with a power supply ranging from 2.7 v to 3.3 v and can be powered down when not in use.
rev. a ? ADF4212L?pecifications 1 (v dd 1 = v dd 2 = 2.7 v to 3.3 v; v p 1, v p 2 = v dd to 5.5 v; agnd rf = dgnd rf = agnd if = dgnd if = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 .) b chips 2 parameter b version typical unit test conditions/comments rf/if characteristics rf input frequency (rf in ) 0.2/2.4 0.2/2.4 ghz min/max for operation below f min , use a square wave rf input sensitivity ?0/0 ?0/0 dbm min/max v dd = 3 v if input frequency (if in ) 100/1000 100/1000 mhz min/max if input sensitivity ?0/0 ?0/0 dbm min/max v dd = 3 v maximum allowable prescaler output frequency 3 200 200 mhz max refin characteristics see figure 2 for input circuit refin input frequency 10/150 10/150 mhz min/max refin input sensitivity 500 mv/v dd 500 mv/v dd v p-p min/max ac-coupled. when dc-coupled, 0 to v dd max (cmos compatible) refin input capacitance 10 10 pf max refin input current ?00 ?00 ? max phase detector phase detector frequency 4 75 75 mhz max charge pump i cp sink/source programmable, see table v high value 5 5 ma typ with r set = 2.7 k ? low value 625 625 ? typ absolute accuracy 2 2 % typ with r set = 2.7 k ? r set range 1.5/5.6 1.5/5.6 k ? min/max i cp three-state leakage current 1 1 na max sink and source current matching 6 6 % typ 0.5 v < v cp < v p ?0.5 v, 2% typ i cp vs. v cp 22 % typ 0.5 v < v cp < v p ?0.5 v i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 1.4 1.4 v min v inl , input low voltage 0.6 0.6 v max i inh /i inl , input current ? ? ? max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage 1.4 1.4 v min open-drain 1 k ? pull-up to 1.8 v v ol , output low voltage 0.4 0.4 v max i ol = 500 ? power supplies v dd 1 2.7/3.3 2.7/3.3 v min/v max v dd 2v dd 1v dd 1 v p 1, v p 2v dd 1/5.5 v dd 1/5.5 v min/v max i dd (rf and if) 5 10 10 ma max 7.5 ma typical rf only 6 6 ma max 5.0 ma typical if only 4 4 ma max 2.5 ma typical i p (i p 1 + i p 2) 0.6 0.6 ma typ low power sleep mode 1 1 ? typ notes 1 operating temperature range is as follows: b version: ?0? to +85?. 2 the b chip specifications are given as typical values. 3 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency less than this value. 4 guaranteed by design. sample tested to ensure compliance. 5 t a = 25?. rf = 1 ghz. prescaler = 32/33. if = 500 mhz. prescaler = 16/17. specifications subject to change without notice.
rev. a ADF4212L ? specifications 1 parameter b version b chips 2 unit test conditions/comments noise characteristics rf phase noise floor 3 ?70 ?70 dbc/hz typ @ 25 khz pfd frequency ?62 ?62 dbc/hz typ @ 200 khz pfd frequency phase noise performance 4 @ vco output if: 540 mhz output 5 ?9 ?9 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency if: 900 mhz output 6 ?7 ?7 dbc/hz typ see note 7 rf: 900 mhz output 6 ?9 ?9 dbc/hz typ see note 7 rf: 1750 mhz output 8 ?4 ?4 dbc/hz typ see note 7 rf: 2400 mhz output 9 ?7 ?7 dbc/hz typ @ 1 khz offset and 1 mhz pfd frequency spurious signals if: 540 mhz output 5 ?8/?0 ?8/?0 db typ @ 200 khz/400 khz and 200 khz pfd frequency if: 900 mhz output 6 ?0/?4 ?0/?4 db typ see note 7 rf: 900 mhz output 6 ?0/?4 ?0/?4 db typ see note 7 rf: 1750 mhz output 8 ?0/?2 ?0/?2 db typ see note 7 rf: 2400 mhz output 9 ?0/?2 ?0/?2 db typ @ 200 khz/400 khz and 200 khz pfd frequency notes 1 operating temperature range is as follows: b version: ?0? to +85? 2 the b chip specifications are given as typical values. 3 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 logn (where n is the n divider value). see tpc 14. 4 the phase noise is measured with the eval-adf4210/12/13eb evaluation board and the hp8562e spectrum analyzer. the spectrum anal yzer provides the refin for the synthesizer (f refout = 10 mhz @ 0 dbm). 5 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f if = 540 mhz; n = 2700; loop b/w = 20 khz 6 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop b/w = 20 khz 7 same conditions as listed on the preceding line. 8 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 1750 mhz; n = 8750; loop b/w = 20 khz 9 f refin = 10 mhz; f pfd = 1 mhz; offset frequency = 1 khz; f rf = 2400 mhz; n = 9800; loop b/w = 20 khz specifications subject to change without notice. timing characteristics * (v dd 1 = v dd 2 = 2.6 v to 3.3 v; v p 1, v p 2 = v dd to 5.5 v; agnd rf = dgnd rf = agnd if = dgnd if = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 .) limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulsewidth * guaranteed by design but not production tested. specifications subject to change without notice. clock data le le t 3 t 1 t 2 t 4 t 5 t 6 db20 (msb) db19 db2 (control bit c2) db1 db0 (lsb) (control bit c1) figure 1. timing diagram (v dd 1 = v dd 2 = 2.7 v to 3.3 v; v p 1, v p 2 = v dd to 5.5 v; agnd rf = dgnd rf = agnd if = dgnd if = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 v.)
rev. a ? ADF4212L caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADF4212L features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2, 3 (t a = 25?, unless otherwise noted.) v dd 1 to gnd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +3.6 v v dd 1 to v dd 2 . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v v p 1, v p 2 to gnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +3.6 v v p 1, v p 2 to v dd 1, v dd 2 . . . . . . . . . . . . . . . . ?.3 v to +3.6 v digital i/o voltage to gnd . . . . . . . ?.3 v to dv dd + 0.3 v analog i/o voltage to gnd . . . . . . . . ?.3 v to v dd + 0.3 v refin, rfin, ifin to gnd . . . . . . . ?.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0? to +85? storage temperature range . . . . . . . . . . . . ?5? to +150? maximum junction temperature . . . . . . . . . . . . . . . . . 150? tssop ja thermal impedance . . . . . . . . . . . . . . 150.4?/w lfcsp ja thermal impedance (paddle soldered) . . 122?/w lfcsp ja thermal impedance (paddle not soldered) 216?/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215? infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220? notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high performance rf integrated circuit with an esd rating of <2 kv, and is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = agnd = dgnd = 0 v ordering guide model temperature range package option * ADF4212Lbru ?0? to +85? ru-20 ADF4212Lbcp ?0? to +85? cp-20 * ru = thin shrink small outline package (tssop) cp = chip scale package (lfcsp) contact the factory for chip availability.
rev. a ADF4212L ? pin configurations lfcsp fl o rf in cp rf a gnd rf dgnd rf 1 2 3 4 5 le r set a gnd if dgnd if 11 if in 12 13 14 15 16 17 18 19 20 cp if v p 2 v dd 2 v p 1 v dd 1 10 9 8 7 6 data clk muxout ref in dgnd if ADF4212L top view (not to scale) tssop ref in clk data le m uxout rf in cp rf fl o a gnd rf v dd 1 dgnd rf v dd 2 v p 1 ADF4212L dgnd if a gnd if if in dgnd if cp if v p 2 1 10 11 20 r set 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 top view (not to scale) pin function description mnemonic description cp rf rf charge pump output. when enabled, this provides ? cp to the external rf loop filter, which in turn drives the external rf vco. dgnd rf digital ground pin for the rf digital circuitry. rf in input to the rf prescaler. this small signal input is normally ac-coupled from the rf vco. agnd rf ground pin for the rf analog circuitry. fl o multiplexed output of rf/if programmable or reference dividers, rf/if fastlock mode. cmos output. ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and an equivalent input resistance of 100 k ? . see figure 2. this input can be driven from a ttl or cmos crystal oscillator, or can be ac-coupled. dgnd if digital ground pin for the if digital, interface, and control circuitry. muxout this multiplexer output allows either the if/rf lock detect, the scaled rf, the scaled if, or the scaled reference frequency to be accessed externally. clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this input is a high impedance cmos input. le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. r set connecting a resistor between this pin and ground sets the maximum rf and if charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is i r cp max set = 13 5 . therefore, with r set = 2.7 k ? , i cp max = 5 ma for both the rf and if charge pumps. agnd if ground pin for the if analog circuitry. if in input to the if prescaler. this small signal input is normally ac-coupled from the if vco. cp if output from the if charge pump. this is normally connected to a loop filter that drives the input to an external vco. v p 2 power supply for the if charge pump. this should be greater than or equal to v dd 2. in systems where v dd 2 is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range up to 5.5 v. v dd 2p ower supply for the if, digital, and interface section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 2 should have a value of between 2.6 v and 3.3 v. v dd 2 must have the same potential as v dd 1. v dd 1p ower supply for the rf section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 1 should have a value of between 2.6 v and 3.3 v. v dd 1 must have the same potential as v dd 2. v p 1 power supply for the rf charge pump. this should be greater than or equal to v dd 1. in systems where v dd 1 is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range up to 5.5 v.
rev. a ? ADF4212L?ypical performance characteristics amplitude ?dbm 0 ? ?0 ?5 ?0 ?5 ?0 0 500 1000 1500 2000 frequency ?mhz 2500 3000 v dd = 3v v p = 5v tpc 1. input sensitivity (rf input) amplitude ?dbm 0 ? ?0 ?5 ?0 ?5 ?0 0 500 1000 1500 frequency ?mhz ?5 v dd = 3v v p = 5v tpc 2. input sensitivity (if input) output power ?db 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?k ?k 1.75g 1k 2k frequency ?hz reference level = ?.2dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds a verages = 22 ?4.2dbc/hz tpc 3. phase noise, rf side (1750 mhz, 200 khz, 20 khz) output power ?db 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?00k ?00k 1.75g 200k 400k reference level = ?.0dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 1hz video bandwidth = 1hz sweep = 2.5 seconds a verages = 20 ?5.9db frequency ?hz tpc 4. reference spurs, rf side (1750 mhz, 200 khz, 20 khz) phase noise ?dbc/hz ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 ?50 100hz 1mhz frequency offset from 1.75ghz carrier 1.38 rms 10db/div rms noise = 1.38 degrees r l = ?0dbc/hz tpc 5. integrated phase noise (1750 mhz, 200 khz/20 khz) output power ?db 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?k ?k 540m 1k 2k reference level = ?.3dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds a verages = 22 ?8.8dbc/hz frequency ?hz tpc 6. phase noise, if side (540 mhz, 200 khz/20 khz)
rev. a ADF4212L ? output power ?db 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?00k ?00k 540m 200k 400k reference level = ?.0dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 1hz video bandwidth = 1hz sweep = 2.5 seconds a verages = 20 ?9.3dbc frequency ?hz tpc 7. reference spurs, if side (540 mhz, 200 khz, 20 khz) phase noise ?dbc/hz ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 ?50 100hz 1mhz frequency offset from 540mhz carrier 0.83 rms 10db/div rms noise = 0.83 degrees r l = ?0dbc/hz tpc 8. integrated phase noise (540 mhz, 200 khz/20 khz) phase detector frequency ?khz 10 10000 phase noise ?dbc/hz 1000 100 v dd = 3v v p = 5v ?30 ?40 ?50 ?60 ?70 ?80 tpc 9. phase noise referred to cp output vs. pfd frequency, rf side phase detector frequency ?khz 10 10000 phase noise ?dbc/hz 1000 100 v dd = 3v v p = 5v ?30 ?40 ?50 ?60 ?70 ?80 tpc 10. phase noise referred to cp output vs. pfd frequency, if side v cp ?v 0 i cp ?ma 1 6 4 2 0 ? ? 2 3 4 5 ? tpc 11. rf charge pump output characteristics v cp ?v 0 i cp ?ma 1 6 4 2 0 ? ? v dd = 3v v p 2 = 5.5v 2 3 4 5 ? tpc 12. if charge pump output characteristics
rev. a ? ADF4212L first reference spur ?dbc 0 ?0 ?0 ?0 ?0 ?00 01 3 5 tuning voltage ?v 2 4 tpc 13. rf reference spurs (200 khz) vs. v tune (1750 mhz, 200 khz, 20 khz) first reference spur ?dbc 0 ?0 ?20 ?0 ?0 ?0 ?00 01234 tuning voltage ?v 5 tpc 14. if reference spurs (200 khz) vs. v tune (1750 mhz, 200 khz, 20 khz) phase noise ?dbc/hz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 20 40 temperature ? c 60 ?0 ?0 ?00 ?0 80 100 tpc 15. rf phase noise vs. temperature (1750 mhz, 200 khz, 20 khz) phase noise ?dbc/hz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 20 40 temperature ? c 60 ?0 ?0 ?00 ?0 80 100 tpc 16. if phase noise vs. temperature (540 mhz, 200 khz, 20 khz) phase noise ?dbc/hz 0 ?0 ?0 ?0 ?0 ?0 ?0 01234 tuning voltage ?v 5 ?0 ?0 ?00 ?0 tpc 17. rf noise vs. v tune phase noise ?dbc/hz 0 ?0 ?0 ?0 ?0 ?0 ?0 01234 tuning voltage ?v 5 ?0 ?0 ?00 ?0 tpc 18. if noise vs. v tune
rev. a ADF4212L ? first reference spur ?dbc 0 ?0 ?0 ?0 ?0 ?0 0 20 40 temperature ? c 100 ?0 ?00 ?20 60 80 tpc 19. rf spurs vs. temperature first reference spur ?dbc 0 ?0 ?0 ?0 ?0 ?0 0 20 40 temperature ? c 100 ?0 ?00 ?20 60 80 tpc 20. if spurs vs. temperature freq ( mhz) 0.561872 0.529742 0.514244 0.405754 0.379354 0.312959 0.322646 0.288881 0.199294 0.206914 0.168344 0.092764 0.036125 0.037007 ?.053842 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 1450 s 11.real s11.imag s11.real s 11.imag ?.021077 ?.110459 ?.085802 ?.185830 ?.245482 ?.282399 ?.305457 ?.358884 ?.541032 ?.585687 ?.482539 ?.530108 ?.590526 ?.592498 ?.655932 0.97692 0.942115 0.961217 0.920667 0.897441 0.888164 0.850012 0.760189 0.767363 0.779511 0.761034 0.624825 0.635364 0.630242 0.634506 1550 1650 1750 1850 1950 2050 2150 2250 2350 2450 2550 2650 2750 2850 2950 ?.648879 ?.668172 ?.702192 ?.714541 ?.703593 ?.802878 ?.803970 ?.807055 ?.758619 ?.725029 ?.770837 ?.778619 ?.706197 ?.716939 ?.736527 freq ( mhz) tpc 21. s parameter data for the rf input circuit description reference input section the reference input stage is shown in figure 2. sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the refin pin on power-down. power-down control ref in nc nc no sw3 sw2 sw1 100k bu ffer to r counter nc = no connect figure 2. reference input stage rf/if input stage the rf/if input stage is shown in figure 3. it is followed by a two-stage limiting amplifier to generate the cml (current mode logic) clock levels needed for the prescaler. 2k 2k 1.6v bias generator rf in a rf in b av dd a gnd figure 3. rf/if input stage
rev. a ?0 ADF4212L prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio, n, to be realized (n = pb + a). the dual modulus prescaler, operating at cml levels, takes the clock from the rf/if input stage and divides it down to a manageable frequency for the cmos a and b counters in the rf and if sections. the prescaler in both sec- tions is programmable. it can be set in software to 8/9, 16/17, 32/33, or 64/65. see table iv and table vi. it is based on a synchronous 4/5 core. rf/if a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feed- back counter. the counters are specified to work when the prescaler output is 200 mhz or less. typically, they will work with 250 mhz output from the prescaler. thus, with an rf input frequency of 2.5 ghz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid. pulse swallow function the a and b counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the equation for the vco frequency is as follows: fpbafr vco refin = () + [] / f vco = output frequency of external voltage controlled oscillator (vco) p =p reset modulus of dual modulus prescaler (8/9, 16/17, and so on) b =p reset divide ratio of binary 13-bit counter (3 to 8191) a = preset divide ratio of binary 6-bit swallow counter (0 to 63) f refin =e xternal reference oscillator frequency r = preset divide ratio of binary 14-bit programmable refer ence counter (1 to 16383) to pfd n = bp + a load load modulus control from rf input stage 12-bit b counter 6-bit a counter prescaler p/p+1 figure 4. rf/if a and b counters rf/if r counter the 14-bit rf/if r counter allows the input reference fre- quency to be divided down to produce the input clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 5 is a simplified schematic. the pfd includes a fixed delay element that sets the width of the antibacklash pulse. this is typically 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and gives a consistent reference spur level. d1 q1 clr1 u1 u3 delay hi up d2 q2 clr2 u2 down +in hi ?n charge pump cp figure 5. rf/if pfd simplified schematic muxout and lock detect the output multiplexer on the ADF4212L allows the user to access various internal points on the chip. the state of muxout is controlled by p3, p4, p11, and p12. see table iii and table v. figure 6 shows the muxout section in block diagram form. lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. it is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. it will stay set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be oper- ated with an external pull-up resistor of 10 k ? nominal. when lock has been detected, it is high with narrow, low-going pulses. if analog lock detect if r counter output if n counter output if/rf analog lock detect rf r counter output rf n counter output rf analog lock detect mux control muxout dv dd dgnd figure 6. muxout schematic
rev. a ADF4212L ?1 table i. c2, c1 truth table control bits c2 c1 data latch 00 if r counter 01 if n counter (a and b) 10 rf r counter 11 rf n counter (a and b) table ii. latch summary 15-bit reference counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (0) c2 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p2 p3 p4 if f o lock detect precision if r counter latch three-state cp if pd polarity p1 if cp current setting db23 ifcp2 db22 ifcp1 db21 ifcp0 r15 12-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (1) c2 (0) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b11 b12 p5 if n counter latch b10 if prescaler db23 p8 db22 p7 db21 p6 b9 if cp gain if power-down 6-bit a counter 15-bit rf reference counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (0) c2 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p10 p11 p12 rf f o rf lock detect rf r counter latch three-state cp rf pd polarity p9 rf cp current setting db23 rfcp2 db22 rfcp1 db21 rfcp0 r15 12-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (1) c2 (1) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b11 b12 p14 rf n counter latch b10 rf prescaler db23 p17 db22 p16 db21 p15 b9 rf cp gain rf power-down 6-bit a counter rf/if input shift register the ADF4212L digital section includes a 24-bit input shift register, a 14-bit if r counter, and an 18-bit if n counter (comprising a 6-bit if a counter and a 12-bit if b counter). also present is a 14-bit rf r counter and an 18-bit rf n counter (comprising a 6-bit rf a counter and a 12-bit rf b counter). data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in the timing dia- gram of figure 1. the truth table for these bits is shown in table i. table ii shows a summary of how the latches are programmed.
rev. a ?2 ADF4212L if r counter latch table iii. if r counter latch map 15-bit if reference counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (0) c2 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p2 p3 p4 if f o lock detect precision three-state cp if pd polarity p1 if cp current setting db23 ifcp2 db22 ifcp1 db21 ifcp0 r15 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 1 2 3 4 . . . 32764 32765 32766 32767 r15 r14 r13 .......... r3 r2 r1 divide ratio 0 1 negative positive p1 if pd polarity 0 1 normal three-state p2 charge pump output 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 logic low state if analog lock detect if reference divider output if n divider output rf analog lock detect rf/if analog lock detect if digital lock detect logic high state rf reference divider output rf n divider output three-state output if counter reset rf digital lock detect rf/if digital lock detect rf counter reset if and rf counter reset p12 p11 p4 p3 muxout from rf r latch 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 i cp (ma) 1.5k 2.7k 5.6k ifcp2 ifcp1 ifcp0 1.1250 2.2500 3.3750 4.5000 5.6250 6.7500 7.7875 9.0000 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 0.301 0.602 0.904 1.205 1.506 1.808 2.109 2.411
rev. a ADF4212L ?3 if n counter latch table iv. if n counter latch map 12-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (1) c2 (0) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b11 b12 p5 b10 if prescaler db23 p8 db22 p7 db21 p6 b9 if cp gain if power-down 6-bit a counter 0 0 . . . 1 1 1 1 0 0 . . . 1 1 1 1 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 1 . . . 1 1 1 1 1 0 . . . 0 0 1 1 1 0 . . . 0 1 0 1 3 4 . . . 4092 4093 4094 4095 b12 b11 b10 b3 b2 b1 b counter divide ratio 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 0 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 60 61 62 63 a6 a5 .......... a2 a1 a counter divide ratio 0 0 1 1 8/9 16/17 32/33 64/65 p6 prescaler value 0 1 0 1 p5 0 1 disabled enabled p7 if power-down 0 1 disabled enabled p8 if cp gain n = bp+a, p is prescaler value set in the function latch b must be greater than or equal to a for contiguous values of n, n min is (p 2 ?p)
rev. a ?4 ADF4212L rf r counter latch table v. rf r counter latch map 15-bit rf reference counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (0) c2 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p10 p11 p12 rf f o rf lock detect three-state cp rf pd polarity p9 rf cp current setting db23 rfcp2 db22 rfcp1 db21 rfcp0 r15 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 1 2 3 4 . . . 32764 32765 32766 32767 r15 r14 r13 .......... r3 r2 r1 divide ratio 0 1 negative positive p9 rf pd polarity 0 1 normal three-state p10 rf charge pump output 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 logic low state if analog lock detect if reference divider output if n divider output rf analog lock detect rf/if analog lock detect if digital lock detect logic high state rf reference divider output rf n divider output three-state output if counter reset rf digital lock detect rf/if digital lock detect rf counter reset if and rf counter reset p12 p11 p4 p3 muxout from if r latch 0 0 0 0 1 1 1 1 rfcp2 0 0 1 1 0 0 1 1 rfcp1 0 1 0 1 0 1 0 1 rfcp0 i cp (ma) 1.5k 1.1250 2.2500 3.3750 4.5000 5.6250 6.7500 7.7875 9.0000 2.7k 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 5.6k 0.301 0.602 0.904 1.205 1.506 1.808 2.109 2.411
rev. a ADF4212L ?5 rf n counter latch table vi. rf n counter latch map 12-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (1) c2 (1) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b11 b12 p14 b10 rf prescaler db23 p17 db22 p16 db21 p15 b9 rf cp gain rf power-down 6-bit a counter 0 0 1 1 8/9 16/17 32/33 64/65 p15 prescaler value 0 1 0 1 p14 0 1 disabled enabled p16 rf power-down 0 1 disabled enabled p17 rf cp gain n = bp+a, p is prescaler value set in the function latch b must be greater than or equal to a for contiguous values of n, n min is (p 2 ?p) 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 0 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 60 61 62 63 a6 a5 .......... a2 a1 a counter divide ratio 0 0 . . . 1 1 1 1 0 0 . . . 1 1 1 1 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 1 . . . 1 1 1 1 1 0 . . . 0 0 1 1 1 0 . . . 0 1 0 1 3 4 . . . 4092 4093 4094 4095 b12 b11 b10 b3 b2 b1 b counter divide ratio
rev. a ?6 ADF4212L program modes table iii and table v show how to set up the program modes in the ADF4212L. the following should be noted: 1. if and rf analog lock detect indicate when the pll is in lock. when the loop is locked and either if or rf analog lock detect is selected, then the muxout pin will show a logic high with narrow, low-going pulses. when the if/rf analog lock detect is chosen, then the locked condition is indicated only when both if and rf loops are locked. 2. the if counter reset mode resets the r and ab counters in the if section and also puts the if charge pump into three- state. the rf counter reset mode resets the r and ab counters in the rf section and also puts the rf charge pump into three-state. the if and rf counter reset mode does both of the above. upon removal of the reset bits, the ab counter resumes counting in close alignment with the r counter. (maximum error is one prescaler output cycle.) 3. the fastlock mode uses muxout to switch a second loop filter damping resistor to ground during fastlock operation. activation of fastlock occurs whenever rf cp gain in the rf reference counter is set to ?. if and rf power-down it is possible to program the adf4210 family for either syn chro- nous or asynchronous power-down on either the if or rf side. synchronous if power-down programming a ??to p7 of the ADF4212L will initiate a power-down. if p2 of the ADF4212L has been set to ??(nor- mal operation), a synchronous power-down is conducted. the device will automatically put the charge pump into three-state and complete the power-down. asynchronous if power-down if p2 of the ADF4212L has been set to ??(three-state the if charge pump) and p7 is subsequently set to ?,?an asynchro nous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the ??to the if power- down bit (p7). synchronous rf power-down programming a ??to p16 of the ADF4212L will initiate a power-down. if p10 of the ADF4212L has been set to ? (normal operation), a synchronous power-down is conducted. the device will automatically put the charge pump into three- state and then complete the power-down. asynchronous rf power-down if p10 of the ADF4212L has been set to ??(three-state the rf charge pump) and p16 is subsequently set to ?,?an asynchro nous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the ??to the rf power- down bit (p16). activation of either synchronous or asynchronous power-down forces the if/rf loop? r and ab dividers to their load state conditions and the if/rf input section is debiased to a high impedance state. the refin oscillator circuit is only disabled if both the if and rf power-downs are set. the input register and latches remain active and are capable of loading and latching data during all power-down modes. the if/rf section of the device will return to normal powered-up operation immediately upon le latching a ??to the appropri- ate power-down bit. if section programmable if reference (r) counter if control bits c2, c1 are 0, 0, the data is transferred from the input shift register to the 14-bit ifr counter. table iii shows the input shift register data format for the ifr counter and the divide ratios possible. if phase detector polarity p1 sets the if phase detector polarity. when the if vco char- acteristics are positive, this should be set to ?.?when they are negative, it should be set to ?.?see table iii. if charge pump three-state p2 puts the if charge pump into three-state mode when pro- grammed to a ?.?it should be set to ??for normal operation. see table iii. if program modes table iii and table v show how to set up the program modes in the ADF4212L. if charge pump currents ifcp2, ifcp1, ifcp0 program current setting for the if charge pump. see table iii. programmable if ab counter if control bits c2, c1 are 0, 1, the data in the input register is used to program the if ab counter. the n counter consists of a 6-bit swallow counter (a counter) and 12-bit programmable counter (b counter). table iv shows the input register data format for programming the if ab counter and the divide ratios possible. if prescaler value p5 and p6 in the if a, b counter latch set the if prescaler values. see table iv. if power-down table iii and table v show the power-down bits in the ADF4212L. if fastlock the if cp gain bit (p8) of the if n register in the ADF4212L is the fastlock enable bit. only when this is ??is if fastlock enabled. when fastlock is enabled, the if cp current is set to maximum value. also, an extra loop filter damping resistor to ground is switched in using the flo pin, thus compensating for the change in loop characteristics while in fastlock. since the if cp gain bit is contained in the if n counter, only one write is needed to both program a new output frequency and initiate fastlock. to come out of fastlock, the if cp gain bit on the if n register must be set to ?.?see table iv.
rev. a ADF4212L ?7 rf section programmable rf reference (r) counter if control bits c2, c1 are 1, 0, the data is transferred from the input shift register to the 14-bit rfr counter. table v shows the input shift register data format for the rfr counter and the divide ratios possible. rf phase detector polarity p9 sets the if phase detector polarity. when the rf vco characteristics are positive, this should be set to ?.?when they are negative, it should be set to ?.?see table v. rf charge pump three-state p10 puts the rf charge pump into three-state mode when pro- grammed to a ?.?it should be set to ??for normal operation. see table v. rf program modes table iii and table v show how to set up the program modes in the ADF4212L. rf charge pump currents rfcp2, rfcp1, and rfcp0 program current setting for the rf charge pump. see table v. programmable rf n counter if control bits c2, c1 are 1, 1, the data in the input register is used to program the rf n (a + b) counter. the n counter consists of a 6-bit swallow counter (a counter) and 12-bit pro- grammable counter (b counter). table iv shows the input register data format for programming the rf n counter and the divide ratios possible. see table vi. rf prescaler value p14 and p15 in the rf a, b counter latch set the rf prescaler values. see table vi. rf power-down table iii and table v show the power-down bits in the adf4210 family. rf fastlock the rf cp gain bit (p17) of the rf n register in the ADF4212L is the fastlock enable bit. only when this is ??is if fastlock enabled. when fastlock is enabled, the rf cp current is set to maximum value. also, an extra loop filter damping resistor to ground is switched in using the flo pin, thus compensating for the change in loop characteristics while in fastlock. since the rf cp gain bit is contained in the rf n counter, only one write is needed to both program a new output frequency and initiate fastlock. to come out of fastlock, the rf cp gain bit on the rf n register must be set to ?.?see table vi. applications local oscillator for gsm handset receiver figure 7 shows the ADF4212L being used with a vco to pro- duce the required los for a gsm base station transmitter or receiver. the reference input signal is applied to the circuit at fref in and, in this case, is terminated in 50 ? . typical gsm systems would have a 13 mhz tcxo driving the reference input without any 50 ? termination. in order to have a channel spacing of 200 khz (the gsm standard), the reference input must be divided by 65, using the on-chip reference. the rf output frequency range is 880 mhz to 915 mhz. the loop filter is designed to give a 20 khz loop bandwidth. the filter is set up for a 5 ma charge pump current, and the vco sensitivity is 12 mhz/v. the if output is fixed at 540 mhz. the filter is again designed to have a bandwidth of 20 khz, and the system is programmed to give channel steps of 200 khz. spi compatible serial bus lock detect vco190-902u v cc cp if if in ref in dgnd rf a gnd rf dgnd if a gnd if clk data le rf in muxout cp rf v p 1 v p 2v dd 2v dd 1 ADF4212L vco190-540t v cc decoupling capacitors (22 f/10pf) on v dd , v p of the ADF4212L and on v cc of the vcos have been omitted from the diagram to aid clarity. 620pf 1.3nf 13nf 100pf 100pf 100pf 100pf 100pf 100pf 18 18 18 51 1.7k 18 18 18 51 3.3k rf out v p v dd v p if out 100pf 100pf 51 fref in 2.7k r set 1nf 8.2nf 620pf 3.3k 5.6k figure 7. gsm handset receiver local oscillator using the ADF4212L
rev. a ?8 ADF4212L wideband pll many of the wireless applications for synthesizers and vcos in plls are narrow-band in nature. these applications include the various wireless standards such as gsm, dsc1800, cdma, or wcdma. in each of these cases, the total tuning range for the local oscillator is less than 100 mhz. however, there are also wideband applications where the local oscillator could have up to an octave tuning range. for example, cable television tuners have a total range of about 400 mhz. figure 8 shows an application where the ADF4212L is used to control and program the micronetics m3500-1324. the loop filter was designed for an rf output of 2100 mhz, a loop bandwidth of 40 khz, a pfd frequency of 1 mhz, i cp of 10 ma (2.5 ma synthesizer i cp multiplied by the gain factor of 4), vco k d of 80 mhz/v (sensitivity of the m3500-1324 at an output of 2100 mhz), and a phase margin of 45 degrees. in narrow-band applications, there is generally a small variation in output frequency (generally less than 10%) and also a small variation in vco sensitivity over the range (typically <10%). however, in wideband applications both of these parameters have a much greater variation, which will change the loop bandwidth. this in turn can affect stability and lock time. by changing the programmable i cp , it is possible to get compensation for these varying loop conditions and to ensure that the loop is always operating close to optimal conditions. ref in dgnd rf a gnd rf dgnd if a gnd if rf in muxout r set v p 1v p 2 v dd 2 v dd 1 ADF4212L spi compatible serial bus clk data le 1000pf 1000pf 51 fref in v dd v p 2.7k lock detect 100pf 51 cp rf ad820 20k 3.9nf 27nf 470 130pf 1k 20v 3k v_tune m3500-1324 gnd v cc out 100pf 18 18 18 100pf rf out decoupling capacitors on v dd , v p of the ADF4212L, on v cc of the ad820 and on v cc of the m3500-2250 have been omitted from the diagram to aid clarity. the if section of the circuit has also been omitted to simplify the schematic. 12v figure 8. wideband pll circuit
rev. a ADF4212L ?9 interfacing the ADF4212L has a simple spi compatible serial interface for writing to the device. sclk, sdata, and le control the data transfer. when le (latch enable) goes high, the 22 bits that have been clocked into the input register on each rising edge of sclk will get transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 909 khz or one update every 1.1 ?. this is certainly more than adequate for systems that will have typical lock times in hun- dreds of microseconds. aduc812 interface figure 9 shows the interface between the ADF4212L and the aduc812 microconverter. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the ADF4212L needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. on first applying power to the ADF4212L, four writes (one each to the r counter latch and the ab counter latch for both if and rf side) are required for the output to become active. when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maxi- mum rate at which the output frequency can be changed will be 180 khz. adsp-2181 interface figure 10 shows the interface between the ADF4212L and the adsp-21xx digital signal processor. as previously discussed, the ADF4212L needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use three memory loca- tions for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. ADF4212L sclk sdata le muxout (lock detect) aduc812 sclk mosi i/o ports ce figure 9. aduc812 to ADF4212L interface ADF4212L sclk muxout (lock detect) adsp-21xx sclk i/o flags sdata dt le tfs ce figure 10. adsp-21xx to ADF4212L interface
rev. a c02774-0-3/03(a) printed in u.s.a. ?0 ADF4212L outline dimensions 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10 20-lead frame chip scale package [lfcsp] 4 mm 4 mm body (cp-20) dimensions shown in millimeters 1 20 5 6 11 16 15 bottom view 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 1.00 max 0.65 nom 0.05 0.02 0.00 1 .00 0.90 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.0 bsc sq coplanarity 0.08 compliant to jedec standards mo-220-vggd-1 0.60 max 0.60 max revision history location page 3/03?ata sheet changed from rev. 0 to rev. a. changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to table iv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 changes to table vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 changes to figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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